1. Field of the Invention
The present invention relates to a semiconductor fabrication process, and more particularly to a method for fabricating an interconnection structure.
2. Description of the Related Art
Recently, copper dual damascene technique with ultra low-k material is the best solution of metal interconnection for fabricating logic integrated circuit chips with high integration and high speed or for semiconductor processes under 0.18 microns. The reason is that copper has a relatively low resistance value (30% less than aluminum) and a relatively good electro-migration resistance, and that the ultra low-k material can make for reducing RC delay between metal wires. Therefore, in the fabrication process of the integrated circuit, the copper dual damascene technique with ultra low-k material is becoming increasingly important.
There are many schemes to fabricate dual damascene structure and the most common integration approaches for the dual damascene architecture are via first, trench first and self-aligned. During the trench first process, a trench is formed in an ultra low k material layer firstly and then a via hole is formed by removing a portion of the ultra low k material layer. Consequently, some polymer produced by the process of forming the via tend to remain at a sidewall and a bottom (that is a surface of the copper metal) of the via hole. The remained polymer may cause some defects of enhancing the resistance value and having RC delay effect. Therefore, before the copper is filled into the via hole, a cleaning process for the trench and the via hole should be carried out firstly, so as to remove the remained polymer at the sidewalls and the bottoms of the trench and the via hole.
Generally, the cleaning process is a dry-cleaning process. That is the remained polymer in the trench and the via hole is removed by a plasma cleaning process. However, because the ultra low-k material layer may react with hydrogen ions and a dielectric coefficient of the ultra low-k material layer would be shifted and increased, a conventional reactive pre-clean (RPC) process is unsuitable for the dual damascene structure having the ultra low-k material layer. Therefore, a plasma cleaning process using argon gas appears. The plasma cleaning process using the argon gas may avoid deviation of the dielectric coefficient of the ultra low-k material layer in the fabrication process, but the fabricated dual damascene structure using the method has a problem of low reliability.
U.S. Pat. No. 6,713,402 disclosed a method for polymer removal following etch-stop layer etch. In the method, after the via hole is formed, the substrate is transferred to a plasma cleaning chamber of about 310° C., and then the hydrogen-containing plasma is introduced to remove the remained polymer. However, in the method of high temperature, some organic gas would be generated. The organic gas not only may affect bonding force between the adjacent layers, but also tends to react with the hydrogen ions to form byproducts. The porous property of the ultra low k material facilitates the byproducts adhering thereon and at the sidewall and the bottom of the via hole, so that a process yield of the dual damascene structure would be decreased.
What is needed, therefore, is a method for fabricating an interconnection structure that can overcome the above-mentioned shortcomings.